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Andrew Kesterson
2026-06-01 12:56:27 -04:00
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04-adc/README.md
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@@ -48,13 +48,13 @@ I really wanted to understand how the ESP32-S3 in particular accomplishes this.
![hold on to your butts](holdontoyourbutts.gif) ![hold on to your butts](holdontoyourbutts.gif)
The ESP32-S3 has two ADCs on the package that both perform in the same fashion. Per the technical reference manual The ESP32-S3 has two ADCs on the package that both perform in the same basic fashion, but are controlled in slightly different ways. Per the technical reference manual
> Two 12-bit Successive Approximation ADCs (SAR ADCs) controlled by five dedicated controllers that can input analog signals from total of 20 channels. The SAR ADCs can operate in a high-performance mode or a low-power mode. > Two 12-bit Successive Approximation ADCs (SAR ADCs) controlled by five dedicated controllers that can input analog signals from total of 20 channels. The SAR ADCs can operate in a high-performance mode or a low-power mode.
![ESP32-S3 SAR ADC diagram](esp32sdcadc.png) ![ESP32-S3 SAR ADC diagram](esp32sdcadc.png)
There are two ADCs on the ESP32-S3, being ADC1 and ADC2. They can both be operated in a low power mode (by driving them with the real-time clock controller) or in a high power mode (using the digital controller). ADC2 is shared among many peripherals such as WiFi, and so it has an "arbiter" hardware component that controls who gets to use it at which times and which controller drives it. ADC1 appears to be dedicated to userland programs running on the CPU, so it does not have a separate hardware arbiter, but you can select which driver to use by controlling a hardware register. There are two ADCs on the ESP32-S3, being ADC1 and ADC2. They can both be operated in a low power mode (by driving them with the real-time clock controller) or in a high power mode (using the digital controller). ADC2 is shared among many peripherals such as WiFi, and so it has an "arbiter" hardware component that controls who gets to use it at which times and which controller drives it. ADC1 appears to be dedicated to userland programs running on the CPU, so it does not have a separate hardware arbiter, it has a much simpler mux device that selects between the RTC and Digital controller based on a hardware register.
### ADC hardware registers ### ADC hardware registers
@@ -62,15 +62,18 @@ The ADC hardware registers are mapped into memory between `0x6000_8000` and `0x6
| ADC | Register | Address | Purpose | | ADC | Register | Address | Purpose |
|-----|----------|---------|---------| |-----|----------|---------|---------|
| ADC1|`SENS_SAR_MEAS1_MUX_REG`|`0x6000_8010`| Selecting the RTC or Digital controller for ADC1 operations|
| ADC1|`SENS_SAR_MEAS1_CTRL2_REG`|`0x6000_800C`| Activating ADC1 and reading the output of the operation|
| ADC1|`SENS_SAR_READER1_CTRL_REG`|`0x6000_8000`| Controlling ADC1 data and sampling| | ADC1|`SENS_SAR_READER1_CTRL_REG`|`0x6000_8000`| Controlling ADC1 data and sampling|
| ADC1|`SENS_SAR_MEAS1_CTRL2_REG`|`0x6000_800C`| Activating ADC1 and reading the output of the operation|
| ADC1|`SENS_SAR_MEAS1_MUX_REG`|`0x6000_8010`| Selecting the RTC or Digital controller for ADC1 operations|
| ADC1|`SENS_SAR_ATTEN1_REG`|`0x6000_8014`| Setting the attenuation for ADC1| | ADC1|`SENS_SAR_ATTEN1_REG`|`0x6000_8014`| Setting the attenuation for ADC1|
|-----|----------|---------|---------|
| ADC2|`SENS_SAR_MEAS2_MUX_REG`|`0x6000_8024`| Selecting the RTC or Digital controller for ADC1 operations| | ADC2|`SENS_SAR_MEAS2_MUX_REG`|`0x6000_8024`| Selecting the RTC or Digital controller for ADC1 operations|
| ADC2|`SENS_SAR_MEAS2_CTRL2_REG`|`0x6000_8030`| Activating ADC1 and reading the output of the operation| | ADC2|`SENS_SAR_MEAS2_CTRL2_REG`|`0x6000_8030`| Activating ADC1 and reading the output of the operation|
| ADC2|`SENS_SAR_READER2_CTRL_REG`|`0x6000_8034`| Controlling ADC1 data and sampling| | ADC2|`SENS_SAR_READER2_CTRL_REG`|`0x6000_8034`| Controlling ADC1 data and sampling|
| ADC2|`SENS_SAR_ATTEN2_REG`|`0x6000_8038`| Setting the attenuation for ADC1| | ADC2|`SENS_SAR_ATTEN2_REG`|`0x6000_8038`| Setting the attenuation for ADC1|
| Both|`SENS_SAR_POWER_XPD_SAR_REG`|`0x6000_803C`| SAR ADC Power Control| | Both|`SENS_SAR_POWER_XPD_SAR_REG`|`0x6000_803C`| SAR ADC Power Control|
## Measuring Capacitance ## Measuring Capacitance