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@@ -89,23 +89,63 @@ As usual the Arduino HAL makes this all really easy and hides a bunch of complex
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All of the ADC hardware is controlled by writing values to the ADC hardware registers. Once these are changed, the ADC hardware sees the change and starts acting on the request.
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All of the ADC hardware is controlled by writing values to the ADC hardware registers. Once these are changed, the ADC hardware sees the change and starts acting on the request.
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The ADC hardware registers are mapped into memory between `0x6000_8000` and `0x6000_8FFF`. These memory addresses are memory mapped in from the low power mode peripherals in the address controller, and are part of the shared instruction/data bus. Basically, when something requests data from those memory regions, the memory address controller redirects the request out to the appropriate peripheral on behalf of whoever is requesting that memory. The peripheral in question then manages the requested item, which is usually stored in a hardware register inside the peripheral. Memory mapped registers are a really common way of controlling peripherals and reduces the complexity of connections between components in the package.
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The hardware registers are all memory mapped in to various regions above `0x5000_0000`. These memory addresses are memory mapped in from the low power mode peripherals in the address controller, and are part of the shared instruction/data bus. Basically, when something requests data from those memory regions, the memory address controller redirects the request out to the appropriate peripheral on behalf of whoever is requesting that memory. The peripheral in question then manages the requested item, which is usually stored in a hardware register inside the peripheral. Memory mapped registers are a really common way of controlling peripherals and reduces the complexity of connections between components in the package.
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The ADC registers that are of most interest to this particular explanation are:
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There are some other registers that I'm not mentioning here, that allow you to do things like set monitors and thresholds on the ADC when it's being driven by the digital controller, that will fire interrpts when they are exceeded. If you really want to dig deep, grab a copy of the ESP32-S3 technical reference manual.
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| ADC | Register | Address | Purpose |
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### Driving the ADC : RTC, Digital, and PWDET
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|-----|----------|---------|---------|
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| ADC1|`SENS_SAR_READER1_CTRL_REG`|`0x6000_8000`| Controlling ADC1 data and sampling|
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| ADC1|`SENS_SAR_MEAS1_CTRL2_REG`|`0x6000_800C`| Activating ADC1 and reading the output of the operation|
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| ADC1|`SENS_SAR_MEAS1_MUX_REG`|`0x6000_8010`| Selecting the RTC or Digital controller for ADC1 operations|
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| ADC1|`SENS_SAR_ATTEN1_REG`|`0x6000_8014`| Setting the attenuation for ADC1|
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| ADC2|`SENS_SAR_MEAS2_MUX_REG`|`0x6000_8024`| Selecting the RTC or Digital controller for ADC1 operations|
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| ADC2|`SENS_SAR_MEAS2_CTRL2_REG`|`0x6000_8030`| Activating ADC1 and reading the output of the operation|
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| ADC2|`SENS_SAR_READER2_CTRL_REG`|`0x6000_8034`| Controlling ADC1 data and sampling|
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| ADC2|`SENS_SAR_ATTEN2_REG`|`0x6000_8038`| Setting the attenuation for ADC1|
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| Both|`SENS_SAR_POWER_XPD_SAR_REG`|`0x6000_803C`| SAR ADC Power Control|
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There are three ways to drive the ADC : using the real time clock driver, the digital driver, or the PWDET driver. ADC1 can use the digital or RTC driver, selected by the user. ADC2 can use the digital, RTC, or PWDET driver, but the mode is controlled by the arbiter hardware device.
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The PWDET driver is the one I know the least about, but I'm sure you can do some nifty stuff with it. Basically it's used only internally to monitor RF power, looks like it's used by the WiFi controller somehow.
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### RTC ADC operation
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#### Hardware Registers
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The ADC RTC hardware registers are mapped into memory between `0x6000_8000` and `0x6000_8FFF`.
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| ADC | Register | Address | Purpose |
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|------|------------------------------|---------------|-------------------------------------------------------------|
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| ADC1 | `SENS_SAR_READER1_CTRL_REG` | `0x6000_8000` | Controlling ADC1 data and sampling |
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| ADC1 | `SENS_SAR_MEAS1_CTRL2_REG` | `0x6000_800C` | Activating ADC1 and reading the output of the operation |
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| ADC1 | `SENS_SAR_MEAS1_MUX_REG` | `0x6000_8010` | Selecting the RTC or Digital controller for ADC1 operations |
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| ADC1 | `SENS_SAR_ATTEN1_REG` | `0x6000_8014` | Setting the attenuation for ADC1 |
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| ADC2 | `SENS_SAR_MEAS2_MUX_REG` | `0x6000_8024` | Selecting the RTC or Digital controller for ADC1 operations |
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| ADC2 | `SENS_SAR_MEAS2_CTRL2_REG` | `0x6000_8030` | Activating ADC1 and reading the output of the operation |
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| ADC2 | `SENS_SAR_READER2_CTRL_REG` | `0x6000_8034` | Controlling ADC1 data and sampling |
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| ADC2 | `SENS_SAR_ATTEN2_REG` | `0x6000_8038` | Setting the attenuation for ADC1 |
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| Both | `SENS_SAR_POWER_XPD_SAR_REG` | `0x6000_803C` | SAR ADC Power Control |
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#### RTC ADC Operation
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The RTC driver lives in the low power portion of the package, so that it can still be driven when the CPU and ULP are asleep. (For example, the System RTC can be configured so that every time it fires, the ULP is awoken from sleep, and it performs various operations, including checking the ADC RTC configuration and firing if it is so configured).
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The RTC operation looks like this:
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* System RTC fires
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* Is ULP asleep? Should I wake it?
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* If no, do nothing with the ADC
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* If yes, ULP is woken up
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* ULP issues an ADP command to the ADC RTC
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* ADC RTC controller has some logic wired in that uses bits from the `SENS_SAR_MEAS1_CTRL2_REG` to determine who can turn it on and when.
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* When `SENS_MEAS1_START_FORCE = 0`, the ULP is allowed to start the ADC RTC Reader.
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* When the `SENS_SAR1_DIG_FORCE` bit of `SENS_SAR_MEAS1_MUX_REG` is unset, the output of the ADC RTC Reader is used for the SAR ADC operation
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* The ADC performs a SAR operation, sets the value in the low word of `SEND_SAR_MEAS1_CTRL2_REG`, and sets the `SENS_MEAS1_DONE_SAR` when the operation is complete and the data is ready
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Since the RTC ADC controller is designed for one-time conversion operations, historically, the RTC pathway is how the HAL drives the ADC for one-shot `analogRead` events. But it varies slightly from the way that the default system timer pathway works.
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* User calls `analogRead`
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* HAL sets the `SENS_MEAS1_START_FORCE` bit of `SENS_SAR_MEAS1_CTRL2_REG` to `1`, which configures the ADC to allow software start requests via the `SENS_MEAS1_START` bit
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* HAL sets the `SENS_MEAS1_START` bit of `SENS_SAR_MEAS1_CTRL2_REG` to `1`, which forces the RTC ADC to fire
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* When the `SENS_SAR1_DIG_FORCE` bit of `SENS_SAR_MEAS1_MUX_REG` is unset, the output of the ADC RTC Reader is used for the SAR ADC operation
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* The ADC performs a SAR operation, sets the value in the low word of `SEND_SAR_MEAS1_CTRL2_REG`, and sets the `SENS_MEAS1_DONE_SAR` when the operation is complete and the data is ready
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####
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## Measuring Capacitance
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## Measuring Capacitance
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