diff --git a/04-adc/README.md b/04-adc/README.md
index 5a60ccd..fa7ccca 100644
--- a/04-adc/README.md
+++ b/04-adc/README.md
@@ -180,7 +180,7 @@ The ADC RTC hardware registers are mapped into memory between `0x6004_0000` and
 | ADC1  | `APB_SARADC_DMA_CONF_REG`          | `0x6004_006C` | DMA configuration register for SAR ADC        |
 | ADC1  | `APB_SARADC_APB_ADC_CLKM_CONF_REG` | `0x6004_0070` | Configure SAR ADC clock                       |
 
-* : I'm guessing somewhat here. The TRM didn't make it clear if these registers were for ADC1 or ADC2, they just numbered them 0 or 1.
+\* : I'm guessing somewhat here. The TRM didn't make it clear if these registers were for ADC1 or ADC2, they just numbered them 0 or 1.
 
 #### Digital ADC Operation