diff --git a/04-adc/README.md b/04-adc/README.md
index 6c90181..d30e078 100644
--- a/04-adc/README.md
+++ b/04-adc/README.md
@@ -66,7 +66,7 @@ The ADC hardware registers are mapped into memory between `0x6000_8000` and `0x6
 | ADC1|`SENS_SAR_MEAS1_CTRL2_REG`|`0x6000_800C`| Activating ADC1 and reading the output of the operation|
 | ADC1|`SENS_SAR_MEAS1_MUX_REG`|`0x6000_8010`| Selecting the RTC or Digital controller for ADC1 operations|
 | ADC1|`SENS_SAR_ATTEN1_REG`|`0x6000_8014`| Setting the attenuation for ADC1|
-|-----|----------|---------|---------|
+| | | | |
 | ADC2|`SENS_SAR_MEAS2_MUX_REG`|`0x6000_8024`| Selecting the RTC or Digital controller for ADC1 operations|
 | ADC2|`SENS_SAR_MEAS2_CTRL2_REG`|`0x6000_8030`| Activating ADC1 and reading the output of the operation|
 | ADC2|`SENS_SAR_READER2_CTRL_REG`|`0x6000_8034`| Controlling ADC1 data and sampling|