andrew/esp32-learning
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

WIP

Browse Source
This commit is contained in:
Andrew Kesterson
2026-06-01 12:56:48 -04:00
parent 45d4c20c58
commit 861d26a168
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
04-adc/README.md
View File

@@ -66,7 +66,7 @@ The ADC hardware registers are mapped into memory between `0x6000_8000` and `0x6
| ADC1|`SENS_SAR_MEAS1_CTRL2_REG`|`0x6000_800C`| Activating ADC1 and reading the output of the operation|
| ADC1|`SENS_SAR_MEAS1_MUX_REG`|`0x6000_8010`| Selecting the RTC or Digital controller for ADC1 operations|
| ADC1|`SENS_SAR_ATTEN1_REG`|`0x6000_8014`| Setting the attenuation for ADC1|
|-----|----------|---------|---------|
| | | | |
| ADC2|`SENS_SAR_MEAS2_MUX_REG`|`0x6000_8024`| Selecting the RTC or Digital controller for ADC1 operations|
| ADC2|`SENS_SAR_MEAS2_CTRL2_REG`|`0x6000_8030`| Activating ADC1 and reading the output of the operation|
| ADC2|`SENS_SAR_READER2_CTRL_REG`|`0x6000_8034`| Controlling ADC1 data and sampling|